Computing devices employ page tables to organize data that is used to translate virtual memory address used by processing devices to physical memory addresses of memory devices. To achieve certain performance goals, computing devices store data of the page tables in cache memory of the processing devices for faster access than access to other memory devices for reading and modifying the page table data.
Page tables are often shared by multiple processing devices so that the processing devices have the same view of and access to a memory device. A processing device, such as a central processing unit (CPU), can change the page table data stored in its cache. To maintain the shared view and access to the memory device, updates for these changes are required to the page table data shared by the other processing devices and the page table data stored in their caches. When page table data is stored locally in caches of the respective processing devices, software of the CPU must perform explicit cache maintenance operations for changes to the page table data before other processing devices access a memory location for which the changed page table data specifies the translation to the physical address of the memory location. These cache maintenance operations incur software maintenance and performance costs that slowdown performance of the computing device. Alternatively, system (or shared) memory management unit (SMMU) page table lookups can be executed via input/output-coherent (IO-coherent) accesses. These IO-coherent accesses experience unbounded quality of service latencies, such as unknown snoop response delays, that cannot be tolerated by real time clients.